52 lines
1008 B
ArmAsm
52 lines
1008 B
ArmAsm
interrupt_vector_table:
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b . @ Reset
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b .
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b . @ SWI instruction
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b .
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b .
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b .
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b .
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b .
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.comm stack, 0x10000 @ Reserve 64k stack in the BSS
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.globl start
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start:
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ldr r0, tt_base
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mcr p15, 0, r0, c2, c0, 0 /* TTBR0 */
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/* Setup page table entries for the page table and kernel (domain 0) */
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ldr r0, tt_tt_addr
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ldr r1, tt_tt_val
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str r1, [r0]
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ldr r0, kernel_tt_addr
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ldr r1, kernel_tt_val
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str r1, [r0]
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/* Set access permissions for domain 0 to "Manager" */
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mov r0, #0x3
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mcr p15, 0, r0, c3, c0, 0 /* DACR */
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/* Enable the MMU */
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mrc p15, 0, r0, c1, c0, 0 /* SCTLR */
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orr r0, r0, #0x1
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mcr p15, 0, r0, c1, c0, 0 /* SCTLR */
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ldr sp, =stack+0x10000 @ Set up the stack
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bl main @ Jump to the main function
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1:
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b 1b @ Halt
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tt_base:
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.word 0x80000000
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tt_tt_addr:
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.word 0x80002000
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tt_tt_val:
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.word 0x80000c02 /* ...c02 means read/write at any priviledge level, and that it's a section w/o PXN bit set */
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kernel_tt_addr:
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.word 0x80002004
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kernel_tt_val:
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.word 0x80100c02
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