interrupt_vector_table:
    b . @ Reset
    b . 
    b . @ SWI instruction
    b . 
    b .
    b .
    b .
    b .

.comm stack, 0x10000 @ Reserve 64k stack in the BSS
.globl start

start:
	ldr r0, tt_base
	mcr p15, 0, r0, c2, c0, 0 /* TTBR0 */

/* Setup page table entries for the page table and kernel (domain 0) */
	ldr r0, tt_tt_addr
	ldr r1, tt_tt_val
	str r1, [r0]

	ldr r0, kernel_tt_addr
	ldr r1, kernel_tt_val
	str r1, [r0]

/* Set access permissions for domain 0 to "Manager" */
	mov r0, #0x3
	mcr p15, 0, r0, c3, c0, 0 /* DACR */

/* Enable the MMU */
	mrc p15, 0, r0, c1, c0, 0 /* SCTLR */
	orr r0, r0, #0x1
	mcr p15, 0, r0, c1, c0, 0 /* SCTLR */

	ldr sp, =stack+0x10000 @ Set up the stack
	bl main @ Jump to the main function

1: 
	b 1b @ Halt

tt_base:
	.word 0x80000000
tt_tt_addr:
	.word 0x80002000
tt_tt_val:
	.word 0x80000c02 /* ...c02 means read/write at any priviledge level, and that it's a section w/o PXN bit set */
kernel_tt_addr:
	.word 0x80002004
kernel_tt_val:
	.word 0x80100c02